1. Field of the Invention
Example embodiments relate to a wafer-level chip-on-chip package and a package on package (PoP), which reduce a mounting height and improve solder joint reliability, and more particularly, to a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique, a method of manufacturing the multi-chip package, a package on package in which a plurality of packages having different functions are vertically stacked and operate in a single system, and a method of manufacturing the package on package.
2. Description of the Related Art
In recent years, as electronic products have become increasingly multifunctional and downscaled, and larger numbers of semiconductor devices per unit volume are being mounted in electronic products. To meet these needs, a system-on-chip (SOC) technique and a system-in-package (SIP) technique have been utilized in semiconductor manufacturing processes.
The SOC technique enables integration of functions of a plurality of semiconductor chips in a single semiconductor chip so that the single semiconductor chip can replace the plurality of semiconductor chips. The SIP technique enables integration of a plurality of individual semiconductor chips in a single semiconductor package so that the single semiconductor package can operate as a single system.
For example, to increase productivity of semiconductor devices, a bump may be formed on a die using a wafer bumping process so that a flip chip can be employed in place of a lead frame. Also, a wafer including a plurality of chips attached to one another may undergo a series of assembling processes, instead of being separated into individual chips, and then be sawed into individual chips, thereby manufacturing a wafer-level package (WLP). In the WLP, the chips may have the same size as the package.
However, a conventional SIP may have an increased mounting area due to horizontal arrangement of a wafer-level package.